2025-00711. Implementation of Additional Due Diligence Measures for Advanced Computing Integrated Circuits; Amendments and Clarifications; and Extension of Comment Period

Vetting For Authorized Integrated Circuit Designer

	Yes/no	If yes, insert how you resolved column 2
Section 1: Legitimacy of the authorized integrated circuit designer:
1.A. Does the entity lack a website?
1.B. Does the entity's website IP address correspond to a different geographical region than the entity's physical address?
1.C. Is the country code of the entity's phone number different than the entity's physical address?
1.D. Does the entity's email address not contain the company domain name?
1.E. Is the entity's physical address invalid?
1.F. Is the entity purportedly a civil end user but its address is co-located with a military “facility”?
1.G. Do publicly available corporate records contradict the entity's assertions regarding its business ( e.g., entity claims to be a large enterprise, but filings show only a small number of employees)?
Section 2: Screening:
2.A. Does the entity's name match an entry in the Consolidated Screening List?
2.B. Does the entity's address match an entry in the Consolidated Screening List?
2.C. Does the customer's senior management or technical leadership ( e.g., process engineers that are team leaders or otherwise leading development or production activities) overlap with an entity on the Consolidated Screening List?
Section 3: Additional Party Screening:
3.A. Are any companies within the entity's corporate hierarchy ( i.e., parent, subsidiary, ultimate beneficial owner) headquartered in Macau or Country Group D:5 in supplement no. 1 to part 740 of the EAR?
3.B. Do any companies within the entity's corporate hierarchy ( i.e., parent, subsidiary, ultimate beneficial owner) match an entry or address in the Consolidated Screening List?
3.C. Are any other parties to the transaction ( e.g., parties described in § 748.5 of the EAR) located or headquartered in Macau or Country Group D:5 in supplement no. 1 to part 740 of the EAR?
Section 4: General Red Flags:
4.A. Is the entity's stated end use inconsistent with the nature of their business?
4.B. Is the requested quantity inconsistent with the entity's size?
4.C. Is a freight forwarding firm listed as the final destination?
4.D. Does the transaction involve multiple freight forwarders located in third countries?
4.E. Has the entity refused to answer questions about the end users and end uses of the product?
4.F. Do supporting documents such as commercial invoices list parties that are not the entity?
4.G. Is the entity overpaying for a product based on known market prices?
4.H Does the transaction involve payments from entities in third countries not otherwise involved in the transaction?

PART 744—CONTROL POLICY: END-USER AND END-USE BASED

18. The authority citation for part 744 continues to read as follows:

Authority: 50 U.S.C. 4801-4852; 50 U.S.C. 4601 et seq.;50 U.S.C. 1701 et seq.;22 U.S.C. 3201 et seq.;42 U.S.C. 2139a; 22 U.S.C. 7201 et seq.;22 U.S.C. 7210; E.O. 12058, 43 FR 20947, 3 CFR, 1978 Comp., p. 179; E.O. 12851, 58 FR 33181, 3 CFR, 1993 Comp., p. 608; E.O. 12938, 59 FR 59099, 3 CFR, 1994 Comp., p. 950; E.O. 13026, 61 FR 58767, 3 CFR, 1996 Comp., p. 228; E.O. 13099, 63 FR 45167, 3 CFR, 1998 Comp., p. 208; E.O. 13222, 66 FR 44025, 3 CFR, 2001 Comp., p. 783; E.O. 13224, 66 FR 49079, 3 CFR, 2001 Comp., p. 786; Notice of September 18, 2024, 89 FR 77011 (September 20, 2024); Notice of November 7, 2024, 89 FR 88867 (November 8, 2024).

19. Section 744.6 is amended by revising paragraph (c)(2)(iii) to read as follows:

§ 744.6

Restrictions on specific activities of “U.S. Persons.”

* * * * *

(c) * * *

(2) * * *

(iii) Semiconductor manufacturing equipment. To or within either Macau or a destination specified in Country Group D:5, any item not subject to the EAR and meeting the parameters of ECCNs 3B001.a.4, c, d, f.1, f.5, f.6, k to ( print page 5312) n, p.2, p.4, r, 3B002.c, 3D992, or 3E992 regardless of end use or end user.

* * * * *

20. Section 744.11 is amended by revising paragraph (a)(2)(v) paragraph heading, paragraphs (a)(2)(v)(A) introductory text, and (a)(2)(v)(A)(1), to read as follows:

§ 744.11

License requirements that apply to entities acting or at significant risk of acting contrary to the national security or foreign policy interests of the United States.

* * * * *

(a) * * *

(2) * * *

(v) Footnote 5 entities and end-user facilities where the “production” of logic or DRAM “advanced-node integrated circuits” occurs.

(A) License requirement. You may not, without a license, reexport, export from abroad, or transfer (in-country) to or within any destination or to any end user or party any foreign-produced item subject to the EAR pursuant to §§ 734.4(a)(9) or 734.9(e)(3), for each of the following paragraphs (A)( 1) through (A)( 4):

( 1) Exports from abroad or reexports from all countries. A license is required for commodities specified in ECCNs 3B001 (except 3B001.a.4, c, d, f.1, f.5, f.6, g, h, k to n, p.2, p.4, or r), 3B002 (except 3B002.c), 3B611, 3B903, 3B991 (except 3B991.b.2.a through 3B991.b.2.b), 3B992, 3B993, or 3B994 when exported from abroad or reexported by an entity headquartered in, or whose ultimate parent company is headquartered in, Macau or a destination specified in Country Group D:5.

* * * * *

PART 748—APPLICATIONS (CLASSIFICATION, ADVISORY, AND LICENSE) AND DOCUMENTATION

21. The authority citation for part 748 continues to read as follows:

Authority: 50 U.S.C. 4801-4852; 50 U.S.C. 4601 et seq.;50 U.S.C. 1701 et seq.;E.O. 13026, 61 FR 58767, 3 CFR, 1996 Comp., p. 228; E.O. 13222, 66 FR 44025, 3 CFR, 2001 Comp., p. 783; Notice of August 13, 2024, 8 FR 66187 (August 15, 2024).

22. Section 748.3 is amended by:

a. Redesignating paragraph (c)(4) as paragraph (c)(5); and

b. Adding a new paragraph (c)(4).

The addition reads as follows:

§ 748.3

Classification requests and advisory opinions.

* * * * *

(c) * * *

(4) To request an addition or modification to or removal from the approved integrated circuit designers list in supplement no. 6 to part 740 of the EAR or the approved “OSAT” companies list in supplement no. 7 to part 740 of the EAR, see § 748.16 of this part.

* * * * *

23. Section 748.16 is added to read as follows:

§ 748.16

Approved integrated circuit designers list and approved “OSAT” companies list, addition, removal, or modification requests.

You must submit an advisory opinion, in accordance with § 748.3 of this part and the provisions in this section, to request an addition or modification to or removal from the approved integrated circuit designers list in supplement no. 6 to part 740 of the EAR, or the approved “OSAT” companies list in supplement no. 7 to part 740 of the EAR. The advisory opinion request must adhere to the provisions in paragraphs (a) through (d) of this section. Denied requests do not result in new license requirements or render the applicant ineligible for license approvals from BIS, nor does a denied request preclude a company from submitting a subsequent request.

(a)(1) Requests to be added. Only entities not headquartered or having an ultimate parent headquartered in Macau or a destination specified in Country Group D:5 in supplement no. 1 to part 740 will be considered for addition to either list. Only entities that have designed, assembled, tested, or packaged integrated circuits, or have credible plans to do so, will be considered for addition to either list. To ensure a thorough review, requests to be added to either list must include the information in supplement no. 4 to this part.

(2) Requests for removal or modification. Any listed party may request to be removed from a list or have their listing modified. If a listed entity's legal status changes ( e.g., is dissolved), then they must request to be removed from the appropriate list. If control of the listed entity changes or the name changes, then the company must submit a modification request. If the company can no longer abide by the provisions of the EAR that pertain to approved entities, then they must request removal from the relevant list.

(3) Submission of requests. All requests should be emailed to [e-mail] with a subject line stating, “Approved supply chain entities request.”

(4) Review of requests for addition, modification, or removal. The End-user Review Committee (ERC) will review all requests (additions, modifications, and removals) to both lists.

(i) The ERC will consider a range of information for requests to be added to a list, potentially including but not limited to such factors as:

(A) the applicant's record of exclusive engagement in appropriate end-use activities;

(B) the applicant's compliance with U.S. export controls;

(C) the need for an on-site review prior to approval;

(D) the applicant's capability of complying with the requirements of being added to the approved integrated circuit designers list or approved “OSAT” companies list;

(E) the ability of the applicant to guard against both the misuse and diversion of computing resources; and

(F) the applicant's relationships with U.S. and foreign companies. In addition, when evaluating the application, the ERC will consider the status of the export controls of the country or countries where the applicant is headquartered, and these countries' support of and adherence to multilateral export control regimes.

(ii) Requests to modify a listing due to a change in ownership or other substantive change to the listed entity will be considered in light of all of the criteria listed above. Requests to modify a listing to correct clerical errors or non-substantive changes to the listed entity's information will typically be approved.

(iii) In reviewing requests to be removed from a list, BIS will consider facts regarding the entity's compliance with the requirements of its status and the entity's rationale for removing its status. In general, requests to be removed from a list will be approved.

(5) Approval status. Approved integrated circuit designer and approved “OSAT” company status ( i.e., listing) is subject to revision, suspension, or revocation entirely or in part.

(6) Continuing representations. Information submitted in an addition or modification request is deemed to constitute continuing representations of existing facts or circumstances. Any material or substantive change relating to the request must be promptly reported to the ERC, whether approved or still under consideration.

(b) Recordkeeping. Records relating to all requests must be retained by the requester in accordance with the recordkeeping requirements set forth in part 762 of the EAR.

(c) Reporting requirements. Authorized integrated circuit designers, to be eligible for that status consistent with Note 1 to ECCN 3A090.a, are required to submit certain information ( print page 5313) to the “front-end fabricator,” which the “front-end fabricator” must then report to BIS. See § 743.9 of the EAR.

(d) Termination of reporting requirements. Approved integrated circuit designers and approved “OSAT” companies may request to be removed from a relevant list, however, the recordkeeping requirements in paragraph (b) of this section and the reporting requirements in paragraph (c) of this section must be adhered to until the listing is removed from the relevant list.

24. Supplement no. 4 is added to read as follows:

Supplement No. 4 to Part 748—Information Required To Be Submitted With a § 748.16 Request

The following information is required to be submitted with a request to be added to either supplement no. 6 to part 740—Approved Integrated Circuit Designer list or supplement no. 7 to part 740—Approved “OSAT” company list, as described in § 748.16. The prospective added integrated circuit designer and prospective approved “OSAT” company are referred to as the candidate in this supplement.

(a) Identity. Name of the candidate, including all names under which the candidate conducts business; complete company physical address (simply listing a post office box is insufficient); telephone number; fax number; email address; company website; and name of individual who should be contacted if BIS has any questions. If the entity submitting the request is different from the candidate identified in the request, this information must be submitted for both entities. If the candidate has multiple locations, all physical addresses must be listed.

(b) Ownership. Provide an overview of the structure, ownership and business of the candidate. Include a description of the entity, including type of business activity, ownership, subsidiaries, and joint-venture projects, as well as an overview of any business activity or corporate relationship that the entity has with either government or military organizations.

(c) “ Applicable advanced logic integrated circuits.” List any “applicable advanced logic integrated circuits” the candidate expects to design, assemble, test, or package, and the end use and any known intended end uses of these commodities. Include a description of the commodities; the ECCN for all commodities, classified to the subparagraph level, as appropriate; and technical parameters for the commodities including performance specifications.

(d) Recordkeeping. Specify how the candidate's record keeping system will allow compliance with the recordkeeping requirements set forth in § 748.16(b) and part 762 of the EAR.

(e) Certification. Include an original statement on letterhead of the candidate, signed and dated by a person who has authority to legally bind the candidate, certifying that the candidate will comply with all the provisions of § 748.16.

(f) Statement of acknowledgement and agreement. The candidate must include this statement of acknowledgement and agreement with the request, that the candidate:

(1) Acknowledges that they have been informed of and understand that the item(s) to be produced by the “front-end fabricator” have been exported in accordance with the EAR and that use or diversion of such items contrary to the EAR is prohibited, particularly the license requirements of §§ 742.6(a)(6)(iii) and 744.23(a)(3) of the EAR;

(2) Agrees to comply with the recordkeeping requirements in § 748.16(b) and part 762 of the EAR; and

(3) Agrees to allow on-site reviews by U.S. Government officials to verify compliance with the EAR.

PART 762—RECORDKEEPING

25. The authority citation for part 762 continues to read as follows:

Authority: 50 U.S.C. 4801-4852; 50 U.S.C. 4601 et seq.;50 U.S.C. 1701 et seq.;E.O. 13222, 66 FR 44025, 3 CFR, 2001 Comp., p. 783.

26. Section 762.2 is amended by adding paragraphs (b)(61) and (b)(62), to read as follows:

§ 762.2

Records to be retained.

* * * * *

(b) * * *

(61) § 748.16(b), all records relating to requests for addition or modifications to or deletion from supplement no. 6 or supplement no. 7 to part 740.

(62) Supplement No. 2 to Part 743 Authorized Integrated Circuit Designer Vetting Form.

* * * * *

PART 772—DEFINITIONS OF TERMS

27. The authority citation for part 772 continues to read as follows:

Authority: 50 U.S.C. 4801-4852; 50 U.S.C. 4601 et seq.;50 U.S.C. 1701 et seq.;E.O. 13222, 66 FR 44025, 3 CFR, 2001 Comp., p. 783.

28. Section 772.1 is amended by:

a. Adding, in alphabetical order, the definitions for “16/14 nanometer node;”

b. Revising the definition for “Advanced-Node Integrated Circuits;”

c. Adding, in alphabetical order, the definitions for “Aggregated approximated transistor count”, “Applicable advanced logic integrated circuits”, “Front-end fabricator”, and “Outsourced Semiconductor Assembly and Test (OSAT)” to read as follows:

§ 772.1

Definitions of terms as used in the Export Administration Regulations (EAR).

* * * * *

16/14 nanometer node (16/14 nm node) is indicated in the Logic Industry “Node Range” figure described in the International Roadmap for Devices and Systems, 2016 edition (“More Moore” White Paper), available at: https://irds.ieee.org/​images/​files/​pdf/​2016_​MM.pdf).

* * * * *

Advanced-Node Integrated Circuits (Advanced-Node IC). For parts 734 and 744 of the EAR, “advanced-node integrated circuits” include integrated circuits that meet any of the following criteria:

(1) Logic integrated circuits using a non-planar transistor architecture or with a “production” `technology node' of 16/14 nanometers or less;

(2) NOT AND (NAND) memory integrated circuits with 128 layers or more; or

(3) Dynamic random-access memory (DRAM) integrated circuits having:

(i) A memory cell area of less than 0.0026 µm² ;

(ii) A memory density greater than 0.20 gigabits per square millimeter; or

(iii) More than 3000 through-silicon vias per die.

Note 1 to definition of “Advanced-Node Integrated Circuits”:

For the purposes of paragraph (1) of this definition, the term technology node refers to the Logic Industry “Node Range” figure described in the International Roadmap for Devices and Systems, 2016 edition (“More Moore” White Paper), available at: >https://irds.ieee.org/​images/​files/​pdf/​2016_​MM.pdf.

Note 2 to definition of “Advanced-Node Integrated Circuits”:

For the purposes of paragraph (3) of this definition, the term memory density refers to the capacity of the monolithic die, package, or stack comprising the DRAM integrated circuit measured in gigabits divided by the relevant area. For a monolithic die, the relevant area is the area of the die. For package or stack, the relevant area is the footprint of the package or stack measured in square millimeters. In the case where a stack is contained in a package, use the area of the package. Cell area is defined as Wordline*Bitline (which takes into consideration both transistor and capacitor dimensions).

* * * * *

Aggregated approximated transistor count means the sum of the `approximated transistor counts,' as defined in Note 1 to 3A090.a, of each “applicable advanced logic integrated circuit” die within the final package fabricated using a “16/14 nanometer node” or below, or using a non-planar transistor architecture.

* * * * *

Applicable advanced logic integrated circuits are logic integrated circuits produced using the “16/14 nanometer ( print page 5314) node” or below, or using a non-planar transistor architecture.

* * * * *

Front-end fabricator is the company that provides front-end fabrication services to produce an integrated circuit, creating circuits on the surface of a wafer through processes such as photolithography, etch, and deposition.

* * * * *

Outsourced Semiconductor Assembly and Test (OSAT) is a company that provides third-party manufacturing and testing services to semiconductor businesses. OSAT companies are responsible for assembling, packaging, and testing integrated circuits and other semiconductor devices.

* * * * *

PART 774—THE COMMERCE CONTROL LIST

29. The authority citation for part 774 continues to read as follows:

Authority: 50 U.S.C. 4801-4852; 50 U.S.C. 4601 et seq.;50 U.S.C. 1701 et seq.;10 U.S.C. 8720; 10 U.S.C. 8730(e); 22 U.S.C. 287c, 22 U.S.C. 3201 et seq.;22 U.S.C. 6004; 42 U.S.C. 2139a; 15 U.S.C. 1824; 50 U.S.C. 4305; 22 U.S.C. 7201 et seq.;22 U.S.C. 7210; E.O. 13026, 61 FR 58767, 3 CFR, 1996 Comp., p. 228; E.O. 13222, 66 FR 44025, 3 CFR, 2001 Comp., p. 783.

30. Supplement no. 1 to part 774 is amended by revising ECCN 3A090, 3B001, 3B993 and 3B994, 3D992, 3D993, 3D994, 3E992, 3E993, and 3E994, to read as follows:

Supplement No. 1 To Part 774—The Commerce Control List

* * * * *

3A090 Integrated circuits as follows (see List of Items Controlled).

License Requirements

Reason for Control: RS, AT

Control(s)	Country chart (see Supp. No. 1 to part 738)
RS applies to entire entry, except 3A090.a	To or within any destination worldwide, see § 742.6(a)(6)(iii)(A) of the EAR.
RS applies to 3A090.b	To or within destinations specified in Country Groups D:1, D:4, and D:5 of supplement no. 1 to part 740 of the EAR, excluding any destination also specified in Country Groups A:5 or A:6. See § 742.6(a)(6)(iii)(B) of the EAR.
RS applies to 3A090.c	To or within Macau or a destination specified in Country Group D:5 of supplement no. 1 to part 740 of the EAR. See § 742.6(a)(6)(i)(B) of the EAR.
AT applies to entire entry	AT Column 1.

List Based License Exceptions (See Part 740 for a Description of All License Exceptions)

LVS: N/A

GBS: N/A

NAC/ACA: Yes, for 3A090.a, if the item is not designed or marketed for use in datacenters and has a `total processing performance' of 4800 or more; yes, for 3A090.b, if the item is designed or marketed for use in datacenters. N/A for 3A090.c.

HBM: Yes, for 3A090.c. See § 740.25 of the EAR.

AIA: Yes, for 3A090.a.

ACM: Yes

LPP: Yes for 3A090.a.

List of Items Controlled

Related Controls: (1) See ECCNs 3D001, 3E001, 5D002.z, and 5D992.z for associated technology and software controls. (2) See ECCNs 3A001.z, 5A002.z, 5A004.z, and 5A992.z.

Related Definitions: N/A

Items:

a. Integrated circuits having one or more digital processing units having either of the following:

a.1. A `total processing performance' of 4800 or more; or

a.2. A `total processing performance' of 1600 or more and a `performance density' of 5.92 or more.

Note 1 to 3A090.a: When a “front-end fabricator” or “OSAT” company is seeking to export, reexport, or transfer (in-country) an “applicable advanced logic integrated circuit,” there is a presumption that the item is 3A090.a and designed or marketed for datacenters. If the “front-end fabricator” or “OSAT” company cannot overcome this presumption, then it must comply with all license requirements applicable to items specified in 3A090.a. However, this presumption does not apply to any entity other than the “front-end fabricator” or “OSAT” company. A “front-end fabricator” or “OSAT” company can overcome this presumption in any of the following three ways outlined in paragraphs a. through c. of this Note 1.

a. If the designer of the “applicable advanced logic integrated circuit” is an approved or authorized integrated circuit designer, then a datasheet or other attestation of the `total processing performance' and the `performance density' from the approved or authorized integrated circuit designer indicating that the IC is not specified in 3A090.a will overcome the presumption for the “front-end fabricator” or “OSAT” company that the IC is specified in ECCN 3A090.a.

(1) Approved integrated circuit designers are listed in supplement no. 6 to this part of the EAR;

(2) Prior to April 13, 2026, authorized integrated circuit designers include all integrated circuit designers:

(i) Headquartered in Taiwan or a destination specified in Country Group A:1 or A:5, that are neither located in nor have an ultimate parent headquartered in Macau or a destination specified in Country Group D:5 of supplement no. 1 to part 740 of the EAR; and

(ii) That have agreed to submit applicable information described in § 743.9(b) to the “front-end fabricator,” which the “front-end fabricator” must then report to BIS.

(3) After April 13, 2026, authorized integrated circuit designers include any integrated circuit designer that both meets the criteria specified in subparagraph (2) and has submitted an application to become an approved integrated circuit designer. However, any company deemed an authorized IC designer after April 13, 2026, will cease to be an authorized IC designer 180 days after the submission of its application to become an approved IC designer.

b. If the integrated circuit die is packaged by the “front-end fabricator” at a location outside of Macau or a destination specified in Country Group D:5 in supplement no. 1 to part 740, then the attestation of the “front-end fabricator” that (a) the “aggregated approximated transistor count” of the final packaged IC is below 30 billion transistors, or (b) the final packaged IC does not contain high-bandwidth memory and that the “aggregated approximated transistor count” of the final packaged IC is below (i) 35 billion transistors for any exports, reexports, or transfers (in-country) completed in 2027; or (ii) 40 billion transistors for any exports, reexports, or transfers (in-country) completed in 2029 or thereafter, then this overcomes the presumption by the “front-end fabricator” or “OSAT” company that the IC is specified in ECCN 3A090.a.

c. If the integrated circuit is packaged by an approved “OSAT” company listed in supplement no. 7 to part 740 of the EAR, then the attestation of the approved “OSAT” company that (a) the “aggregated approximated transistor count” of the final packaged IC is below 30 billion transistors, or (b) the final packaged IC does not contain high-bandwidth memory and that the “aggregated approximated transistor count” of the final packaged IC is below (i) 35 billion transistors for any exports, reexports, or transfers (in-country) completed in 2027; or (ii) 40 billion transistors for any exports, reexports, or transfers (in-country) completed in 2029 or thereafter, then this overcomes the presumption by the “front-end fabricator” or “OSAT” company that the IC is specified in ECCN 3A090.a.

d. It is not sufficient for the “front-end fabricator” or “OSAT” company to confirm the ECCN by relying on the attestation of the end user or other party to the transaction, except under one of the three ways enumerated in paragraphs a. through c. of this note. In the absence of an attestation of the `total processing performance' and the `performance density' by an approved integrated circuit designer listed in supplement no. 6 to part 740 of the EAR, the “front-end fabricator” or “OSAT” company must presume that any logic integrated circuit produced using the “16/14 nanometer node” or below, or using a non-planar transistor architecture and destined for a commodity with an (a) “aggregated ( print page 5315) approximated transistor count” of the final packaged IC is below 30 billion transistors, or (b) the final packaged IC does not contain high-bandwidth memory and that the “aggregated approximated transistor count” of the final packaged IC is below (i) 35 billion transistors for any exports, reexports, or transfers (in-country) completed in 2027; or (ii) 40 billion transistors for any exports, reexports, or transfers (in-country) completed in 2029 or thereafter, or where the “aggregated approximated transistor count,” of the final, packaged integrated circuit cannot be confirmed by the “front-end fabricator,” or an approved “OSAT” company listed in supplement no. 7 to part 740 of the EAR, is specified in ECCN 3A090.a and designed or marketed for a datacenter.

Technical Note 1 to 3A090.a: The `approximated transistor count' of a die is the `transistor density' of the die multiplied by the area of the die measured in square millimeters. The `transistor density' of the die is the number of transistors that can be fabricated per square millimeter for the process node used to manufacture the die. To calculate the number of `approximated transistor count' of a die, a “front end fabricator” or “OSAT” company has two options. First, the “front end fabricator” or “OSAT” company may take the transistor density of the process node used to manufacture the die and multiply this density by the area of the die. This number may be significantly higher than the true transistor count, but if the result is below the relevant transistor threshold, then the “front end fabricator” or “OSAT” company can be confident that the die in question will not exceed that threshold. Second, to adjudicate edge cases, the “front end fabricator” or “OSAT” company may use standard design verification tools to estimate the number of (both active and passive) transistors on the die using the GDS file.

b. Integrated circuits having one or more digital processing units having either of the following:

b.1. A `total processing performance' of 2400 or more and less than 4800 and a `performance density' of 1.6 or more and less than 5.92, or

b.2. A `total processing performance' of 1600 or more and a `performance density' of 3.2 or more and less than 5.92.

Note 2 to 3A090.a and 3A090.b: 3A090.a and 3A090.b do not apply to items that are not designed or marketed for use in datacenters and do not have a `total processing performance' of 4800 or more. For 3A090.a and 3A090.b items that are not designed or marketed for use in datacenters and that have a `total processing performance' of 4800 or more, see license exceptions NAC and ACA.

Note 3 to 3A090.a and 3A090.b: Integrated circuits specified by 3A090 include graphical processing units (GPUs), tensor processing units (TPUs), neural processors, in-memory processors, vision processors, text processors, co-processors/accelerators, adaptive processors, field-programmable logic devices (FPLDs), and application-specific integrated circuits (ASICs). Examples of integrated circuits are in the Note to 3A001.a.

Note 4 to 3A090.a and 3A090.b: For integrated circuits that are excluded from ECCN 3A090 under Note 2 or 3 to 3A090, those ICs are also not applicable for classifications made under ECCNs 3A001.z, 4A003.z, 4A004.z, 4A005.z, 4A090, 5A002.z, 5A004.z, 5A992.z, 5D002.z, or 5D992.z because those other CCL classifications are based on the incorporation of an integrated circuit that meets the control parameters under ECCN 3A090 or otherwise meets or exceeds the control parameters or ECCNs 3A090 or 4A090. The performance parameters under ECCN 3A090.c are not used for determining whether an item is classified in a .z ECCN. See the Related Controls paragraphs of ECCNs 3A001.z, 4A003.z, 4A004.z, 4A005.z, 4A090, 5A002.z, 5A004.z, 5A992.z, 5D002.z, or 5D992.z.

Technical Note 2 to 3A090.a and 3A090.b:

1. `Total processing performance' (`TPP') is 2 × `MacTOPS' × `bit length of the operation', aggregated over all processing units on the integrated circuit.

a. For purposes of 3A090, `MacTOPS' is the theoretical peak number of Tera (10¹² ) operations per second for multiply-accumulate computation (D = A × B + C).

b. The 2 in the `TPP' formula is based on industry convention of counting one multiply-accumulate computation, D = A × B + C, as 2 operations for purpose of datasheets. Therefore, 2 × MacTOPS may correspond to the reported TOPS or FLOPS on a datasheet.

c. For purposes of 3A090, `bit length of the operation' for a multiply-accumulate computation is the largest bit-length of the inputs to the multiply operation.

d. Aggregate the TPPs for each processing unit on the integrated circuit to arrive at a total. `TPP' = TPP1 + TPP2 + . . . . + TPPn (where n is the number or processing units on the integrated circuit).

2. The rate of `MacTOPS' is to be calculated at its maximum value theoretically possible. The rate of `MacTOPS' is assumed to be the highest value the manufacturer claims in annual or brochure for the integrated circuit. For example, the `TPP' threshold of 4800 can be met with 600 tera integer operations (or 2 × 300 `MacTOPS') at 8 bits or 300 tera FLOPS (or 2 × 150 `MacTOPS') at 16 bits. If the integrated circuit is designed for MAC computation with multiple bit lengths that achieve different `TPP' values, the highest `TPP' value should be evaluated against parameters in 3A090.

3. For integrated circuits specified by 3A090 that provide processing of both sparse and dense matrices, the `TPP' values are the values for processing of dense matrices (e.g., without sparsity).

4. `Performance density' is `TPP' divided by `applicable die area'. For purposes of 3A090, `applicable die area' is measured in millimeters squared and includes all die area of logic dies manufactured with a process node that uses a non-planar transistor architecture.

c. High bandwidth memory (HBM) having a `memory bandwidth density' greater than 2 gigabytes per second per square millimeter.

Technical Note 1 to 3A090.c: `Memory bandwidth density' is the memory bandwidth measured in gigabytes per second divided by the area of the package or stack measured in square millimeters. In the case where a stack is contained in a package, use the memory bandwidth of the packaged device and the area of the package. High bandwidth memory (HBM) includes dynamic random access memory integrated circuits, regardless of whether they conform to the JEDEC standards for high bandwidth memory (HBM), provided they have a `memory bandwidth density' greater than 2 gigabytes per second per square millimeter. This control does not cover co-packaged integrated circuits with both HBM and logic integrated circuit where the dominant function of the co-packaged integrated circuit is processing. It does include HBM permanently affixed to a logic integrated circuit designed as a control interface and incorporating a physical layer (PHY) function.

* * * * *

3B001 Equipment for the manufacturing of semiconductor devices, materials, or related equipment, as follows (see List of Items Controlled) and “specially designed” “components” and “accessories” therefor.

License Requirements

Reason for Control: NS, RS, AT

Control(s)	Country chart (see Supp. No. 1 to part 738)
NS applies to 3B001.c.1.a, 3B001.c.1.c, and 3B001.q	Worldwide control. See § 742.4(a)(5) and (b)(10) of the EAR.
RS applies to 3B001.c.1.a, 3B001.c.1.c, and 3B001.q	Worldwide control. See § 742.6(a)(10) and (b)(11) of the EAR.
NS applies to 3B001.a.1 to a.3, b, e, f.2 to f.4, g to j	NS Column 2.
NS applies to 3B001.a.4, c, d, f.1, f.5, f.6, k to n, p.2, p.4, r	To or within Macau or a destination specified in Country Group D:5 of supplement no. 1 to part 740 of the EAR. See § 742.4(a)(4) of the EAR.
RS applies to 3B001.a.4, c, d, f.1, f.5, f.6, k to n, p.2, p.4, r	To or within Macau or a destination specified in Country Group D:5 of supplement no. 1 to part 740 of the EAR. See § 742.6(a)(6) of the EAR.
AT applies to entire entry	AT Column 1.

List Based License Exceptions (See Part 740 for a Description of All License Exceptions)

LVS: $500, except semiconductor manufacturing equipment specified in 3B001.a.4, c, d, f.1, f.5, f.6, k to n, p.2, p.4, r.

GBS: Yes, except a.3 (molecular beam epitaxial growth equipment using gas sources), c.1.a (Equipment designed or modified for isotropic dry etching), c.1.c (Equipment designed or modified for anisotropic dry etching), .e (automatic loading multi-chamber central wafer handling systems only if connected to equipment controlled by 3B001.a.3, or .f), .f (lithography equipment) and .q (“EUV” masks and reticles designed for integrated circuits, not specified by 3B001.g, and ( print page 5316) having a mask “substrate blank” specified by 3B001.j).

IEC: Yes, for 3B001.c.1.a, c.1.c, and .q, see § 740.2(a)(22) and § 740.24 of the EAR.

Special Conditions for STA

STA: License Exception STA may not be used to ship 3B001.c.1.a, c.1.c, and .q to any of the destinations listed in Country Group A:5 or A:6 (See supplement no. 1 to part 740 of the EAR).

List of Items Controlled

Related Controls: See also 3B903 and 3B991. See ECCNs 3D001, 3D992, 3E001, and 3E992 for related “software” and “technology” controls.

Related Definitions: N/A

Items:

a. Equipment designed for epitaxial growth as follows:

a.1. Equipment designed or modified to produce a layer of any material other than silicon with a thickness uniform to less than ±2.5% across a distance of 75 mm or more;

Note: 3B001.a.1 includes atomic layer epitaxy (ALE) equipment.

a.2. Metal Organic Chemical Vapor Deposition (MOCVD) reactors designed for compound semiconductor epitaxial growth of material having two or more of the following elements: aluminum, gallium, indium, arsenic, phosphorus, antimony, oxygen, or nitrogen;

a.3. Molecular beam epitaxial growth equipment using gas or solid sources;

a.4. Equipment designed for epitaxial growth of silicon (Si) or silicon germanium (SiGe), and having all of the following:

a.4.a. At least one preclean chamber designed to provide a surface preparation means to clean the surface of the wafer; and

a.4.b. An epitaxial deposition chamber designed to operate at a temperature equal to or below 958 K (685 °C).

b. Semiconductor wafer fabrication equipment designed for ion implantation and having any of the following:

b.1. [Reserved]

b.2. Being designed and optimized to operate at a beam energy of 20 keV or more and a beam current of 10 mA or more for hydrogen, deuterium, or helium implant;

b.3. Direct write capability;

b.4. A beam energy of 65 keV or more and a beam current of 45 mA or more for high energy oxygen implant into a heated semiconductor material “substrate”; or

b.5. Being designed and optimized to operate at beam energy of 20 keV or more and a beam current of 10mA or more for silicon implant into a semiconductor material “substrate” heated to 600 °C or greater;

c. Etch equipment.

c.1. Equipment designed for dry etching as follows:

c.1.a. Equipment designed or modified for isotropic dry etching, having a largest ‘silicon germanium-to-silicon (SiGe:Si) etch selectivity' of greater than or equal to 100:1; or

c.1.b. [Reserved]

c.1.c. Equipment designed or modified for anisotropic dry etching, having all of the following;

c.1.c.1. Radio Frequency (RF) power source(s) with at least one pulsed RF output;

c.1.c.2. One or more fast gas switching valve(s) with switching time less than 300 milliseconds; and

c.1.c.3. Electrostatic chuck with twenty or more individually controllable variable temperature elements;

c.2. Equipment designed for wet chemical processing and having a largest ‘silicon germanium-to-silicon (SiGe:Si) etch selectivity' of greater than or equal to 100:1;

c.3. Equipment designed for anisotropic dry etching having all of following:

c.3.a Two or more RF independent sources;

c.3.b Two or more independent gas sources;

c.3.c `Process uniformity tuning' for wafer thickness variation compensation; and

c.3.d Through Silicon Via (TSV) reveal Endpoint Detection (EPD);

c.4. Equipment designed for Through Silicon Via (TSV) etch having all of the following:

c.4.a. Silicon etch rate greater than 7 microns per minute;

c.4.b. Within wafer (WIW) etch depth non-uniformity of less than or equal 2 percent; and

c.4.c. A Through Silicon Via (TSV) aspect ratio greater than or equal to 10:1.

Note 1: 3B001.c includes etching by `radicals', ions, sequential reactions, or non-sequential reaction.

Note 2: 3B001.c.1.c includes etching using RF pulse excited plasma, pulsed duty cycle excited plasma, pulsed voltage on electrodes modified plasma, cyclic injection and purging of gases combined with a plasma, plasma atomic layer etching, or plasma quasi-atomic layer etching.

Technical Notes:

1. For the purposes of 3B001.c, ‘silicon germanium-to-silicon (SiGe:Si) etch selectivity' is measured for a Ge concentration of greater than or equal to 30% (Si_0.70 Ge_0.30).

2. For the purposes of 3B001.c Note 1 and 3B001.d.14, `radical' is defined as an atom, molecule, or ion that has an unpaired electron in an open electron shell configuration.

3. For the purposes of 3B001.c.3, `process uniformity tuning' is the process of compensating for incoming wafer thickness variations after grinding.

d. Semiconductor manufacturing deposition equipment, as follows:

d.1. Equipment designed for cobalt (Co) electroplating or cobalt electroless-plating deposition processes;

Note: 3B001.d.1 controls semiconductor wafer processing equipment.

d.2. Equipment designed for:

d.2.a. Chemical vapor deposition of cobalt (Co) fill metal; or

d.2.b. Selective bottom-up chemical vapor deposition of tungsten (W) fill metal;

d.3. Semiconductor manufacturing equipment designed to fabricate a metal contact by multistep processing within a single chamber by performing all of the following:

d.3.a. Deposition of a tungsten layer, using an organometallic compound, while maintaining the wafer substrate temperature greater than 100 °C and less than 500 °C; and

d.3.b. Surface treatment plasma process using hydrogen (H2), hydrogen and nitrogen (H2+N2), or ammonia (NH3).

d.4. Equipment or systems designed for multistep processing in multiple chambers or stations, as follows:

d.4.a. Equipment designed to fabricate a metal contact by performing all of the following processes:

d.4.a.1. Surface treatment plasma process using hydrogen (H₂), including hydrogen and nitrogen (H₂ + N₂) or ammonia (NH₃), while maintaining the wafer substrate at a temperature greater than 100 °C and less than 500 °C;

d.4.a.2. Surface treatment plasma process using oxygen (O₂) or ozone (O₃), while maintaining the wafer substrate at a temperature greater than 40 °C and less than 500 °C; and

d.4.a.3. Deposition of a tungsten (W) layer while maintaining the wafer substrate temperature greater than 100 °C and less than 500 °C;

d.4.b. Equipment designed to fabricate a metal contact by performing all of the following processes:

d.4.b.1 Surface treatment process using a remote plasma generator and an ion filter; and

d.4.b.2. Deposition of a cobalt (Co) layer selectively onto copper (Cu) using an organometallic compound;

Note: This control does not apply to equipment that is non-selective.

d.4.c. Equipment designed to fabricate a metal contact by performing all the following processes:

d.4.c.1. Deposition of a titanium nitride (TiN) or tungsten carbide (WC) layer, using an organometallic compound, while maintaining the wafer substrate at a temperature greater than 20 °C and less than 500 °C;

d.4.c.2. Deposition of a cobalt (Co) layer using a physical sputter deposition technique and having a process pressure greater than 133.3 mPa and less than 13.33 Pa, while maintaining the wafer substrate at a temperature below 500 °C; and

d.4.c.3. Deposition of a cobalt (Co) layer using an organometallic compound and having a process pressure greater than 133.3 Pa and less than 13.33 kPa, while maintaining the wafer substrate at a temperature greater than 20 °C and less than 500 °C;

d.4.d. Equipment designed to fabricate copper (Cu) interconnects by performing all of the following processes:

d.4.d.1. Deposition of a cobalt (Co) or ruthenium (Ru) layer using an organometallic compound and having a process pressure greater than 133.3 Pa and less than 13.33 kPa, while maintaining the wafer substrate at a temperature greater than 20 °C and less than 500 °C; and

d.4.d.2. Deposition of a copper layer using a physical vapor deposition technique and having a process pressure greater than 133.3 mPa and less than 13.33 Pa, while maintaining the wafer substrate at a temperature below 500 °C;

d.5. Equipment designed for plasma enhanced chemical vapor deposition of carbon hard masks more than 2 um thick and with density of greater than 1.7g/cc; ( print page 5317)

d.6. Atomic Layer Deposition (ALD) equipment designed for area selective deposition of a barrier or liner using an organometallic compound;

Note: 3B001.d.6 includes equipment capable of area selective deposition of a barrier layer to enable fill metal contact to an underlying electrical conductor without a barrier layer at the fill metal via interface to an underlying electrical conductor.

d.7. Equipment designed for Atomic Layer Deposition (ALD) of tungsten (W) to fill an entire interconnect or in a channel less than 40 nm wide, while maintaining the wafer substrate at a temperature less than 500 °C.

d.8. Equipment designed for Atomic Layer Deposition (ALD) of `work function metal' having all of the following:

d.8.a. More than one metal source of which one is designed for an aluminum (Al) precursor;

d.8.b. Precursor vessel designed and enabled to operate at a temperature greater than 30 °C; and

d.8.c. Designed for depositing a ‘work function metal' having all of the following:

d.8.c.1. Deposition of titanium-aluminum carbide (TiAlC); and

d.8.c.2. Enabling a work function greater than 4.0 eV;

Technical Note: For the purposes of 3B001.d.8, ‘work function metal' is a material that controls the threshold voltage of a transistor.

d.9. Spatial Atomic Layer Deposition (ALD) equipment having a wafer support platform that rotates around an axis having any of the following:

d.9.a. A spatial plasma enhanced atomic layer deposition mode of operation;

d.9.b. A plasma source; or

d.9.c. A plasma shield or means to confine the plasma to the plasma exposure process region;

d.10. Equipment designed for Atomic Layer Deposition (ALD) or Chemical Vapor Deposition (CVD) of plasma enhanced of low fluorine tungsten (FW) (fluorine (F) concentration less than 10¹⁹ atoms/cm³ ) films;

d.11. [Reserved]

d.12. Equipment designed for depositing a metal layer, and having any of the following:

d.12.a. Selective tungsten (W) growth without a barrier; or

d.12.b. Selective molybdenum (Mo) growth without a barrier;

d.13. Equipment designed for depositing a ruthenium layer (Ru) using an organometallic compound, while maintaining the wafer substrate at a temperature greater than 20 °C and less than 500 °C;

d.14. Equipment designed for deposition assisted by remotely generated ‘radicals', enabling the fabrication of a silicon (Si) and carbon (C) containing film, and having all of the following properties of the deposited film:

d.14.a. A dielectric constant (k) of less than 4.4;

d.14.b. In features with an aspect ratio greater than 5:1 with lateral openings of less than 35 nm; and

d.14.c. A feature-to-feature pitch of less than 45 nm;

d.15. Equipment designed for void free plasma enhanced deposition of a low-k dielectric layer in gaps between metal lines less than 25 nm and having an aspect ratio greater than or equal to 1:1 with a less than 3.3 dielectric constant;

d.16. [Reserved]

d.17. Equipment designed for plasma enhanced chemical vapor deposition (PECVD) or radical assisted chemical vapor deposition and UV curing in a single platform of a dielectric film, while maintaining a substrate temperature below 500 °C, having all of the following:

d.17.a. A thickness of more than 6 nm and less than 20 nm on metal features having less than 24 nm pitch and having an aspect ratio equal to or greater than 1:1.8; and

d.17.b. A dielectric constant less than 3.0;

d.18. Equipment designed or modified for Atomic Layer Deposition (ALD) of molybdenum (Mo), ruthenium (Ru), or combinations Mo or Ru, and having all of the following:

d.18.a. A metal precursor source designed or modified to operate at a temperature greater 75 °C; and

d.18.b. A process chamber (module) using a reducing agent containing hydrogen (H) at a pressure greater than or equal to 30 Torr (4 kPa).

Note: For the purposes of paragraph d.18.a, the metal precursor source need not be integrated with the equipment. The metal precursor could be delivered by an on-tool source or from a sub-fab source.

d.19. Deposition equipment having direct-liquid injection of more than two metal precursors, designed or modified to deposit a conformal dielectric film with a dielectric constant (K) greater than 40 in features with aspect ratio greater than 200:1 in a single deposition chamber.

d.20. Physical vapor deposition equipment having electromagnets for ion flux guidance, and “specially designed” to deposit tungsten (W) metal into features having an aspect ratio of 3:1 or greater.

e. Automatic loading multi-chamber central wafer handling systems having all of the following:

e.1. Interfaces for wafer input and output, to which more than two functionally different ‘semiconductor process tools' controlled by 3B001.a, .b., .c, and .d are designed to be connected; and

e.2. Designed to form an integrated system in a vacuum environment for ‘sequential multiple wafer processing';

Note: 3B001.e does not control automatic robotic wafer handling systems “specially designed” for parallel wafer processing.

Technical Notes:

1. For the purposes of 3B001.e, ‘semiconductor process tools' refers to modular tools that provide physical processes for semiconductor “production” that are functionally different, such as deposition, implant or thermal processing.

2. For the purposes of 3B001.e, ‘sequential multiple wafer processing' means the capability to process each wafer in different ‘semiconductor process tools', such as by transferring each wafer from one tool to a second tool and on to a third tool with the automatic loading multi-chamber central wafer handling systems.

f. Lithography commodities as follows:

f.1. Align and expose step and repeat (direct step on wafer) or step and scan (scanner) equipment for wafer processing using photo-optical or X-ray methods and having any of the following:

f.1.a. A light source wavelength shorter than 193 nm; or

f.1.b. A light source wavelength equal to or longer than 193 nm and having all of the following:

f.1.b.1. The capability to produce a pattern with a “Minimum Resolvable Feature size” (MRF) of 45 nm or less; and

f.1.b.2. A maximum `dedicated chuck overlay' value of less than or equal to 1.50 nm;

Technical Notes: For the purposes of 3B001.f.1.b:

1. The ‘Minimum Resolvable Feature size' (MRF) ( i.e., resolution) is calculated by the following formula:

( print page 5318)

where, for the purposes of 3B001.f.1.b, the K factor = 0.25 ‘MRF' is also known as resolution.

2. ‘Dedicated chuck overlay' is the alignment accuracy of a new pattern to an existing pattern printed on a wafer by the same lithographic system. ‘Dedicated chuck overlay' is also known as single machine overlay.

f.2. Imprint lithography equipment capable of production features of 45 nm or less;

Note: 3B001.f.2 includes:

— Micro contact printing tools

— Hot embossing tools

— Nano-imprint lithography tools

— Step and flash imprint lithography (S-FIL) tools

f.3. Equipment “specially designed” for mask making having all of the following:

f.3.a. A deflected focused electron beam, ion beam or “laser” beam; and

f.3.b. Having any of the following:

f.3.b.1. A Full-Width Half-Maximum (FWHM) spot size smaller than 65 nm and an image placement less than 17 nm (mean + 3 sigma); or

f.3.b.2. [Reserved]

f.3.b.3. A second-layer overlay error of less than 23 nm (mean + 3 sigma) on the mask;

f.4. Equipment designed for device processing using direct writing methods, having all of the following:

f.4.a. A deflected focused electron beam; and

f.4.b. Having any of the following:

f.4.b.1. A minimum beam size equal to or smaller than 15 nm; or

f.4.b.2. An overlay error less than 27 nm (mean + 3 sigma);

f.5. Imprint lithography equipment having an overlay accuracy less (better) than 1.5;

f.6. Commodities not specified by 3B001.f.1, designed or modified to perform all of the following in or with deep-ultraviolet immersion photolithography equipment:

f.6.a. Decrease the minimum resolvable feature specified by 3B001.f.1.b; and

f.6.b. Decrease the maximum `dedicated chuck overlay' of a deep-ultraviolet immersion lithography tool below or equal to 1.5 nm.

g. Masks and reticles, designed for integrated circuits controlled by 3A001;

h. Multi-layer masks with a phase shift layer not specified by 3B001.g and designed to be used by lithography equipment having a light source wavelength less than 245 nm;

Note: 3B001.h does not control multi-layer masks with a phase shift layer designed for the fabrication of memory devices not controlled by 3A001.

N.B.: For masks and reticles, “specially designed” for optical sensors, see 6B002.

i. Imprint lithography templates designed for integrated circuits by 3A001;

j. Mask “substrate blanks” with multilayer reflector structure consisting of molybdenum and silicon, and having all of the following:

j.1. “Specially designed” for “Extreme Ultraviolet” (“EUV”) lithography; and

j.2. Compliant with SEMI Standard P37;

k. Equipment designed for ion beam deposition or physical vapor deposition of a multi-layer reflector for “EUV” masks;

l. “EUV” pellicles;

m. Equipment for manufacturing “EUV” pellicles;

n. Equipment designed for coating, depositing, baking, or developing photoresist formulated for “EUV” lithography;

o. [Reserved]

p. Removal and cleaning equipment as follows:

p.1. [Reserved]

p.2. Single wafer wet cleaning equipment with surface modification drying; or

p.3. [Reserved]

p.4. Equipment designed for single wafer cleaning using supercritical CO₂ or sublimation drying;

q. “EUV” masks and “EUV” reticles, designed for integrated circuits, not specified by 3B001.g, and having a mask “substrate blank” specified by 3B001.j; or

Technical Notes: For the purposes of 3B001.q, masks or reticles with a mounted pellicle are considered masks and reticles.

r. Equipment designed for EUV `pattern shaping.'

Technical Note: For the purposes of 3B001.r, ‘pattern shaping’ is a deposition or removal process used to improve overall patterning by reshaping or trimming patterns produced using EUV lithography with non-vertical directed particles including ions, neutral particles, clusters, radicals, or light.

* * * * *

3B993 Specified semiconductor manufacturing equipment as follows (see list of items controls), and “specially designed” “components” and “accessories” therefor.

License Requirements

Reason for Control: RS, AT

Control(s)	Country chart (see Supp. No. 1 to part 738)
RS applies to entire entry	See § 742.6(a)(11) of the EAR.
AT applies to entire entry	AT Column 1.

List Based License Exceptions (See Part 740 for a Description of All License Exceptions)

LVS: N/A

GBS: N/A

List of Items Controlled

Related Controls: (1) See ECCNs 3D993 and 3E993 for associated “software” and “technology” controls. (2) For additional controls that apply to this ECCN, see also § 744.11(a)(2)(v) and § 744.23(a)(4) of the EAR.

Related Definitions: N/A

Items:

a. [Reserved]

b. Semiconductor wafer fabrication equipment for 300 mm wafers designed for ion implantation and having any of the following:

b.1. Equipment designed for plasma doping, having all of the following:

b.1.a. One or more Radio Frequency (RF) power source(s);

b.1.b. One or more pulsed DC Power Source; and

b.1.c. One or more n-type or p-type dopant implants.

b.2 [Reserved]

c. Etch equipment as follows:

c.1. Equipment designed or modified for anisotropic etching of dielectric materials and enabling the fabrication of high aspect ratio features with aspect ratio greater than 30:1 and a lateral dimension on the top surface of less than 100 nm, and having all of the following:

c.1.a. Radio Frequency (RF) power source(s) with at least one pulsed RF output; and

c.1.b. One or more fast gas switching valve(s) with switching time less than 300 milliseconds.

Note: 3B993.c.1 includes etching by ‘radicals’, ions, sequential reactions, or non-sequential reaction.

Technical Note: For the purposes of the Note to 3B993.c.1, ‘radical’ is defined as an atom, molecule, or ion that has an unpaired electron in an open electron shell configuration.

c.2. Equipment, not specified by 3B993.c.1, designed for anisotropic etching of dielectric material and enabling the fabrication of high aspect ratio features having all of the following:

c.2.a. An aspect ratio greater than 30:1; and

c.2.b. A lateral dimension on the top surface of less than 40 nm.

Note: 3B993.c.2 does not apply to equipment designed for wafer diameters less than 300 mm.

c.3. Equipment, not specified by 3B001.c.1.c, designed or modified for anisotropic dry etching, having all of the following:

c.3.a. Radio Frequency (RF) power source(s) with at least one pulsed RF output;

c.3.b. One or more fast gas switching valve(s) with switching time less than 500 milliseconds; and

c.3.c. Electrostatic chuck with greater than or equal to 10 individually controllable variable temperature elements.

d. Semiconductor manufacturing deposition equipment as follows:

d.1. Equipment designed, not specified by 3B001.d.14, for deposition assisted by remotely generated `radicals', enabling the fabrication of a silicon (Si) and carbon (C) containing film, and having all of the following properties of the deposited film:

d.1.a. A dielectric constant (k) of less than 5.3;

d.1.b. In features with an aspect ratio greater than 5:1 with lateral openings of less than 70 nm; and

d.1.c. A feature-to-feature pitch of less than 100 nm.

d.2. Equipment designed for deposition of a film, containing silicon and carbon, and having a dielectric constant (k) of less than 5.3, into lateral openings having widths of less than 70 nm and aspect ratios greater than 5:1 (depth: width) and a feature-to-feature pitch of less than 100 nm, while maintaining the wafer substrate at a temperature greater than 400 °C and less than 650 °C, and having all of the following:

d.2.a. Boat designed to hold multiple vertically stacked wafers;

d.2.b. Two or more vertical injectors; and

d.2.c. A silicon source and propene are introduced to a different injector than a nitrogen source or an oxygen source. ( print page 5319)

d.3. Equipment designed for chemical vapor deposition of a carbon material layer with a density more than 1.6 g/cm³ .

d.4. Deposition equipment, not specified by 3B001.d.19, having direct-liquid injection of more than two metal precursors, designed or modified to deposit a conformal dielectric film with a dielectric constant (K) greater than 35 in features with aspect ratio greater than 50:1 in a single deposition chamber.

e. [Reserved]

f. Lithography commodities as follows:

f.1. Align and expose step and repeat (direct step on wafer) or step and scan (scanner) lithography equipment for wafer processing using photo-optical or X-ray methods and having all of the following:

f.1.a. [Reserved]

f.1.b. A light source wavelength equal to or longer than 193 nm and having all of the following:

f.1.b.1 The capability to produce a pattern with a `Minimum Resolvable Feature size' (`MRF') of 45 nm or less; and

f.1.b.2. A maximum ‘dedicated chuck overlay' value greater than 1.50 nm and less than or equal to 2.40 nm.

Technical Notes for paragraph 3B993.f.1:

1. The ‘Minimum Resolvable Feature size' (‘MRF') is calculated by the following formula:

where, for the purposes of 3B993.f.1, the K factor = 0.25.

`MRF' is also known as resolution.

2. `Dedicated chuck overlay' is the alignment accuracy of a new pattern to an existing pattern printed on a wafer by the same lithographic system. `Dedicated chuck overlay' is also known as single machine overlay.

f.2. Imprint lithography equipment having an overlay accuracy above 1.5 nm and less (better) than or equal to 4.0 nm.

f.3. Commodities designed or modified to increase the number of wafers processed per hour, averaged over any time interval, by greater than 1%, of equipment specified in 3B001.f.1 or 3B993.f.1.

f.4. Commodities not specified by 3B993.f.1 designed or modified to perform all of the following in or with deep-ultraviolet immersion photolithography equipment:

f.4.a. Decrease the minimum resolvable feature specified by 3B993.f.1.b.1; and

f.4.b. Decrease the maximum `dedicated chuck overlay' of deep-ultraviolet immersion lithography equipment above 1.5 nm and below or equal to 2.4 nm.

g. through n. [Reserved]

o. Annealing equipment designed for 300 mm wafers as follows:

o.1 Annealing equipment, operating in a vacuum (equal to or less than 0.01 Pa) environment, performing any of the following:

o.1.a Reflow of copper (Cu) to minimize or eliminate voids or seams in copper (Cu) metal interconnects; or

o.1.b Reflow of cobalt (Co) or tungsten (W) fill metal to minimize or eliminate voids or seams;

o.2. Equipment designed to heat a semiconductor wafer to a temperature greater than 1000 °C (1832 °F) for a `duration' less than 2 ms.

Technical Note: For the purposes of 3B993.o.2, `duration' is the period above stated temperature.

p. Removal and cleaning equipment as follows:

p.1. Equipment designed for removing polymeric residue and copper oxide (CuO) film and enabling deposition of copper (Cu) metal in a vacuum (equal to or less than 0.01 Pa) environment.

p.2. [Reserved]

p.3. Equipment designed for dry surface oxide removal preclean or dry surface decontamination.

Note to 3B993.p.1 and p.3: These controls do not apply to deposition equipment.

q. Inspection and metrology equipment as follows:

q.1. Patterned wafer defect metrology or patterned wafer defect inspection equipment, designed or modified to accept wafers greater than or equal to 300 mm in diameter, and having all of the following:

q.1.a. Designed or modified to detect defects having a size equal to or less than 21 nm; and

q.1.b. Having any of the following:

q.1.b.1. A light source with an optical wavelength less than 400 nm;

q.1.b.2. An electron-beam source with a resolution less (better) than or equal to 1.65 nm;

q.1.b.3. A Cold Field Emission (CFE) electron-beam source; or

q.1.b.4. Two or more electron-beam sources.

q.2. Metrology equipment as follows:

q.2.a. Stand-alone equipment designed to measure wafer shape parameters prior to lithography exposure and utilize measurements to improve overlay or focus of a deep ultraviolet (DUV) lithography system having an immersion lens having a numerical aperture more than 1.3 or an Extreme Ultraviolet lithography (EUV) system; or

q.2.b. Metrology equipment designed to measure focus or overlay after resist development or after etch on product wafers using image-based overlay or diffraction-based measurements techniques, with an overlay measurement accuracy less (better) than or equal to 0.5 nm having any of the following:

q.2.b.1 designed for integration to a `track'; or

q.2.b.2 `fast wavelength switching functionality';

Technical Notes:

1. For the purposes of 3B993.q.2, a `track' is equipment designed for coating and developing photoresist formulated for lithography.

2. For the purposes of 3B993.q.2, `fast wavelength switching functionality' is defined as having the ability the change the measurement wavelength and acquire a measurement in less than 25 ms.

* * * * *

3B994 Semiconductor manufacturing equipment that enables “advanced-node integrated circuit” production, as follows (see list of items controls), and “specially designed” “components” and “accessories” therefor.

License Requirements

Reason for Control: RS, AT

Control(s)	Country chart (see Supp. No. 1 to part 738)
RS applies to entire entry	See § 742.6(a)(11) of the EAR.
AT applies to entire entry	AT Column 1.

List Based License Exceptions (See Part 740 for a Description of All License Exceptions)

LVS: N/A

GBS: N/A

Special Conditions for STA

STA: License Exception STA may not be used to ship or transmit commodities specified in this ECCN to any of the destinations listed in Country Group A:5 or A:6 (See supplement no.1 to part 740 of the EAR).

List of Items Controlled

Related Controls: (1) See ECCNs 3D994 and 3E994 for associated software and technology controls. (2) For additional controls that apply to this ECCN, see also § 744.11(a)(2)(v) and § 744.23(a)(4) of the EAR.

Related Definitions: N/A

Items:

Note for 3B994: Equipment specified in this ECCN 3B994 are limited to equipment designed for volume production, such as equipment designed to accept a SEMI standard wafer carrier such as a 200 mm or larger Front Opening Unified Pod or be connected to a multi-chamber wafer handling system.

a. [Reserved] ( print page 5320)

b. Semiconductor wafer fabrication equipment designed for ion implantation of 300mm wafers as follows:

b.1. [Reserved]

b.2. Ion implantation equipment as follows:

b.2.a. Having all of the following:

b.2.a.1. Beam current greater than 1uA and less than 5mA; and

b.2.a.2. Beam energy greater than 5 keV and less than 300 keV; or

b.2.b. Having all of the following:

b.2.b.1. Beam current greater than 5 mA; and

b.2.b.2. Beam energy less than 5 keV; or

b.2.c. Having angular accuracy equal to or less (better) than 0.1 degrees.

c. through p. [Reserved]

q. Inspection and metrology equipment as follows:

q.1. and q.2. [Reserved]

q.3. Optical thin film metrology equipment or optical critical dimension metrology equipment designed for 300mm wafers and containing software designed for measuring non-planar transistors.

* * * * *

3D992 “Software” for the “development” or “production” of commodities specified in 3B001.a.4, c, d, f.1, f.5, f.6, k to n, p.2, p.4, r, or 3B002.c and “software” as follows (see List of Items Controlled).

License Requirements

Reason for Control: NS, RS, AT

Control(s)	Country chart (see Supp. No. 1 to part 738)
NS applies to the entire entry	To or within Macau or a destination specified in Country Group D:5 of supplement no. 1 to part 740 of the EAR. See § 742.4(a)(4) of the EAR.
RS applies to the entire entry	To or within Macau or a destination specified in Country Group D:5 of supplement no. 1 to part 740 of the EAR. See § 742.6(a)(6)(i) of the EAR.
NS applies to “software” for equipment controlled by 3B001.c.1.a or c.1.c	Worldwide control. See § 742.4(a)(5) and (b)(10) of the EAR.
RS applies to “software” for equipment controlled by 3B001.c.1.a or c.1.c	Worldwide control. See § 742.6(a)(10) and (b)(11) of the EAR.
AT applies to entire entry	AT Column 1.

List Based License Exceptions (See Part 740 for a Description of All License Exceptions)

TSR: N/A

IEC: Yes, for “software” for equipment controlled by 3B001.c.1.a and 3B001.c.1.c, see § 740.2(a)(22) and § 740.24 of the EAR.

Special Conditions for STA

STA: License Exception STA may not be used to ship or transmit “software” specified in this ECCN to any of the destinations listed in Country Group A:5 or A:6 (See supplement no.1 to part 740 of the EAR).

List of Items Controlled

Related Controls: For additional controls that apply to this ECCN, see also § 744.11(a)(2)(v) and (a)(3) and § 744.23(a)(4)(iii) of the EAR.

Related Definitions: N/A

Items:

a. “Software” “specially designed” for the “development” or “production,” of commodities specified in 3B001.a.4, c, d, f.1, f.5, f.6, k to n, p.2, p.4, r, or 3B002.c.

b. ‘Electronic Computer-Aided Design’ (‘ECAD’) “software” designed for the integration of multiple dies into a ‘multi-chip’ integrated circuit, and having all of the following:

b.1. Floor planning; and

b.2. Co-design or co-simulation of die and package.

Technical Note: For the purposes of 3D992.b, ‘multi-chip’ includes multi-die and multi-chiplet.

c. “Software” not specified by 3D992.a designed or modified to perform all of the following in or with deep-ultraviolet immersion photolithography equipment:

c.1. Decrease the minimum resolvable feature specified by 3B001.f.1.b; and

c.2. Decrease the maximum ‘dedicated chuck overlay’ of deep-ultraviolet immersion lithography equipment below or equal to 1.5 nm.

3D993 “Software” for the “development” or “production” of commodities specified in 3B993 and “software” as follows (see List of Items Controlled).

License Requirements

Reason for Control: RS, AT

Control(s)	Country chart (see Supp. No. 1 to part 738)
RS applies to entire entry	See § 742.6(a)(11) of the EAR.
AT applies to entire entry	AT Column 1.

List Based License Exceptions (See Part 740 for a Description of All License Exceptions)

TSR: N/A

Special Conditions for STA

STA: License Exception STA may not be used to ship or transmit “software” specified in this ECCN to any of the destinations listed in Country Group A:5 or A:6 (see supplement no.1 to part 740 of the EAR).

List of Items Controlled

Related Controls: For additional controls that apply to this ECCN, see also § 744.11(a)(2)(v) and (a)(3) and § 744.23(a)(4)(iii) of the EAR.

Related Definitions: N/A

Items:

a. “Software” “specially designed” for the “development” or “production” of commodities specified in 3B993.

b. ‘Electronic Computer-Aided Design’ (‘ECAD’) “software” designed or modified for the “development” or “production” of integrated circuits using multipatterning.

c. ‘Computational lithography’ “software” designed or modified for the “development” or “production” of patterns on DUV lithography masks or reticles.

Technical Note: For the purposes of 3D993, ‘computational lithography’ is the use of computer modelling to predict, correct, optimize and verify imaging performance of the lithography process over a range of patterns, processes, and system conditions.

d. “Software” designed or modified to increase the number of wafers processed per hour, averaged over any time interval, by greater than 1%, of equipment specified in 3B001.f.1 or 3B993.f.1.

e. “Software” not specified by 3D993.a designed or modified to perform all of the following in or with deep-ultraviolet immersion photolithography equipment:

e.1. Decrease the minimum resolvable feature specified by 3B993.f.1.b.1; and

e.2. Decrease the maximum ‘dedicated chuck overlay’ of deep-ultraviolet immersion lithography equipment above 1.5 nm and below or equal to 2.4 nm.

3D994 “Software” “specially designed” for the “development” or “production” of commodities specified in 3B994 and “software” as follows (see List of Items Controlled).

License Requirements

Reason for Control: RS, AT

Control(s)	Country chart (see Supp. No. 1 to part 738)
RS applies to entire entry	See § 742.6(a)(11) of the EAR.
AT applies to entire entry	AT Column 1.

List Based License Exceptions (See Part 740 for a Description of All License Exceptions)

TSR: N/A

Special Conditions for STA

STA: License Exception STA may not be used to ship or transmit “software” specified in this ECCN to any of the destinations listed in Country Group A:5 or A:6 (see supplement no. 1 to part 740 of the EAR).

List of Items Controlled

Related Controls: For additional controls that apply to this ECCN, see also § 744.11(a)(2)(v) and (a)(3) and § 744.23(a)(4)(iii) of the EAR.

Related Definitions: N/A

Items: The list of items controlled is contained in the ECCN heading.

* * * * *

3E992 “Technology” for the “production” or “development” of commodities specified in 3B001.a.4, c, d, f.1, f.5, f.6, k to n, p.2, p.4, r; and 3B002.c; and “technology” as follows (see List of Items Controlled).

License Requirements

Reason for Control: NS, RS, AT ( print page 5321)

Control(s)	Country chart (see Supp. No. 1 to part 738)
NS applies to the entire entry	To or within Macau or a destination specified in Country Group D:5 of supplement no. 1 to part 740 of the EAR. See § 742.4(a)(4) of the EAR.
RS applies to the entire entry	To or within Macau or a destination specified in Country Group D:5 of supplement no. 1 to part 740 of the EAR. See § 742.6(a)(6)(i) of the EAR.
NS applies to “software” for equipment controlled by 3B001.c.1.a or c.1.c	Worldwide control. See § 742.4(a)(5) and (b)(10) of the EAR.
RS applies to “software” for equipment controlled by 3B001.c.1.a or c.1.c	Worldwide control. See § 742.6(a)(10) and (b)(11) of the EAR.
AT applies to entire entry	AT Column 1.

List Based License Exceptions (See Part 740 for a Description of All License Exceptions)

TSR: N/A

IEC: Yes, for “technology” for equipment controlled by 3B001.c.1.a, and 3B001.c.1.c, see § 740.2(a)(22) and § 740.24 of the EAR.

Special Conditions for STA

STA: License Exception STA may not be used to ship or transmit “technology” specified in this ECCN to any of the destinations listed in Country Group A:5 or A:6 (see supplement no. 1 to part 740 of the EAR).

List of Items Controlled

Related Controls: N/A

Related Definitions: N/A

Items:

a. “Technology” “specially designed” for the “development” or “production” of commodities specified in 3B001.a.4, c, d, f.1, f.5, f.6, k to n, p.2, p.4, r; or 3B002.c.

b. “Technology” not specified by 3E992.a designed or modified to perform all of the following in or with deep-ultraviolet immersion photolithography equipment:

b.1. Decrease the minimum resolvable feature specified by 3B001.f.1.b; and

b.2. Decrease the maximum ‘dedicated chuck overlay’ of deep-ultraviolet immersion lithography equipment below or equal to 1.5 nm.

3E993 “Technology” for the “development” or “production” of commodities specified in 3B993; and “technology” as follows (see List of Items Controlled).

License Requirements

Reason for Control: RS, AT

Control(s)	Country chart (see Supp. No. 1 to part 738)
RS applies to entire entry	See § 742.6(a)(11) of the EAR.
AT applies to entire entry	AT Column 1.

List Based License Exceptions (See Part 740 for a Description of All License Exceptions)

TSR: N/A

Special Conditions for STA

STA: License Exception STA may not be used to ship or transmit “technology” specified in this ECCN to any of the destinations listed in Country Group A:5 or A:6 (see supplement no. 1 to part 740 of the EAR).

List of Items Controlled

Related Controls: For additional controls that apply to this ECCN, see also § 744.11(a)(2)(v) and (a)(3) and § 744.23(a)(4)(iii) of the EAR.

Related Definitions: N/A

Items:

a. “Technology” “specially designed” for the “development” or “production” of commodities specified by 3B993.

b. “Technology” designed or modified to increase the number of wafers processed per hour, averaged over any time interval, by greater than 1%, of equipment specified in 3B001.f.1 or 3B993.f.1.

c. “Technology” not specified by 3E993.a designed or modified to perform all of the following in or with deep-ultraviolet immersion photolithography equipment:

c.1. Decrease the minimum resolvable feature specified by 3B993.f.1.b.1; and

c.2. Decrease the maximum ‘dedicated chuck overlay’ of a deep-ultraviolet immersion lithography equipment above 1.5 nm and below or equal to 2.4 nm.

3E994 “Technology” “specially designed” for the “development” or “production” of commodities specified in 3B994 and “technology” as follows (see List of Items Controlled).

License Requirements

Reason for Control: RS, AT

Control(s)	Country chart (see Supp. No. 1 to part 738)
RS applies to entire entry	See § 742.6(a)(11) of the EAR.
AT applies to entire entry	AT Column 1.